The present invention relates to a structure of a flash memory and a method for manufacturing the same, and more particularly, to a structure of a flash memory cell with source/drain programming and erasing and a method for manufacturing the same.
As semiconductor process technologies continue enhancing, computers, telecommunication products, network products, and information appliances (IA) are developed vigorously. By scaling down device size, not only the integration of circuit devices can be increased, and the cost can be reduced, but also the performance, such as the changing speed of devices and the power consumption of devices, can be then improved, and the functions thereof, such as data storage, logic operation, and information processing, can be enhanced. Therefore, to scale down the size of semiconductor devices is the primary motivation to drive the semiconductor process technologies. Especially, for semiconductor memory devices that have a very important share in the market have strict demands about the diminution of device size.
As the increasing popularization of portable electric devices, imperious demands for light, handy, and dependable storage devices are induced. Regardless of digital cameras, notebooks, personal digital assistants (PDA), or mobile phones, etc, they all need a dependable and convenient method to store and transmit data. Because a flash memory is a kind of a non-volatile memory, and the data stored in the flash memory can be kept after the power is shut off, flash memory devices are widely applied in the portable electric products.
Referring to FIG. 1, FIG. 1 shows a cross-sectional view of a conventional stacked gate flash memory cell structure. In a flash memory cell 100, a tunneling oxide layer 108, a floating gate 110, a dielectric layer 112, and a control gate 114 of the flash memory cell 100 are stacked and formed on the semiconductor substrate 102 in sequence. A source 104 and a drain 106 of the flash memory cell 100 are formed by a thermal diffusion method or an ion implantation method to dope ions into the substrate 102. Typically, the floating gate 110 and the control gate 114 are composed of polysilicon, and thus the dielectric layer 112 is called as an inter-poly dielectric (IPD) layer. Besides, the dielectric layer 112 is usually formed by stacking three material layers, i.e. oxide/nitride/oxide (ONO), thereby to provide a better blocking ability for preventing the chargers within the floating gate 110 from entering the control gate 114.
Usually, the programming of the flash memory cell 100 is performed by a channel hot electron injection (CHEI) method. For example, the channel hot electron injection method is to set the substrate 102 and the source 104 to 0 V, and the drain 106 to about 3 V, and to connect the control gate 114 to a power of high voltage, such as 12 V. After conducting, the electrons of the source 104 are driven by the voltage of the drain 106 to pass through the channel region 105 and move toward the drain 106. The energy of electrons is increased by the acceleration from the high channel electric field, during the electrons passing through the channel region 105. Especially in the region that is adjacent to the drain 106, the energy of electrons is greatly increased, thereby inducing the hot electron effect. As a result of the hot electron effect, a part of the electrons have enough energy to exceed the potential barrier of the tunneling oxide layer 108. The attraction resulted from the high voltage of the control gate 114 drives the electrons to pass through the tunneling oxide layer 108 and inject into the floating gate 110, so as to complete the programming of the data.
In addition, the erasing action of the flash memory cell 100 is performed by a Fowler-Nordheim (FN) tunneling effect. The FN tunneling effect erasing method can be divided into a channel erasing method and a source/drain erasing method. In the channel erasing method, the control gate 114 is supplied with a negative voltage or is grounded, and the channel region 105 is supplied with a high voltage, such as 12 V, thereby attracting the electrons trapped within the floating gate 110 into the channel region 105 to complete the data erasing. In the source/drain erasing method, the control gate 114 is supplied with a negative voltage or is grounded, and the source 104 and/or the drain 106 are supplied with a high voltage, such as 12 V, thereby attracting the electrons trapped within the floating gate 110 into the source 104 and/or the drain 106 to complete the data erasing.
As semiconductor process technologies continue enhancing, although the supplied voltage needed for performing the programming and erasing of the flash memory cell 100 is reduced, yet, the electric field for programming and erasing the flash memory cell 100 still needs the same intensity. Without changing the programming/erasing voltage of the flash memory cell 100, it is very difficult to achieve the desired voltage of programming/erasing while the supplied voltage is reduced. At present, there are two methods can be used to reduce the programming/erasing voltage of the flash memory cell 100. The first method is to decrease the thickness of the tunneling oxide layer 108, and the second method is to increase the capacitor coupling ratio between the control gate 114 and the floating gate 110.
Since the thickness of the tunneling oxide layer 108 multiplies the electric field used to program/erase the flash memory cell 100 is proportional to the voltage for programming/erasing the flash memory cell 100, decreasing the thickness of the tunneling oxide layer 108 can reduce the voltage for programming/erasing the flash memory cell 100. However, in order to keep the reliability of the flash memory cell 100, the thickness of the tunneling oxide layer 108 is preferred to be more than 80 xc3x85, and is about 100 xc3x85 more preferably. Hence, there is not much room left for decreasing the thickness of the tunneling oxide layer 108. In addition, increasing the capacitor coupling ratio between the control gate 114 and the floating gate 110 can increase the floating gate 110 voltage coupled from the control gate 114, so that the voltage needed to be supplied to program/erase the flash memory cell 100 can be reduced. However, in the typical process of the flash memory cell 100, increasing the capacitor coupling ratio between the control gate 114 and the floating gate 110 usually leads to an increase in the size of the flash memory cell 100 and the process cost.
Furthermore, since there is not much room left for decreasing the thickness of the tunneling oxide layer 108, when the supplied voltage is reduced, the electrons ejecting from the source 104 though the channel region 105 to the drain 106 cannot be controlled effectively. Especially, as the device size continues reducing to make the gate region decrease continuously, so that the leakage current of the sub-channel area far from the gate under the channel region 105 is getting more serious. Particularly, for the flash memory cell 100 using the source/drain erasing method, the source 104/drain 106 needs a larger junction depth. Thus, the leakage current is getting worse.
According to the aforementioned conventional flash memory cell structure, the leakage current between a source and a drain is getting worse, especially using a source/drain programming/erasing method of a FN tunneling effect. In addition, using a conventional method to manufacture a flash memory cell, the coupling capacitor between a control gate and a floating gate cannot be increased effectively without increasing the cell size and the processing cost.
Therefore, one major object of the present invention is to provide a structure of a flash memory cell having a horizontal surrounding gate and formed on a trench. A channel of the flash memory cell is a semiconductor film traversing over a portion of the trench, and surrounded and encompassed by a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate in sequence, so that the current of the flash memory cell of the present invention can be conducted in the both sides of the channel region. Besides, the floating gate and the control gate are also formed in a hollow region between the channel and the bottom of the trench, thereby effectively improving the leakage current between a source and a drain, and increasing the current of the flash memory cell at on-state. Moreover, by increasing the depth of the trench, the overlap area between the floating gate and the control gate can be increased, so that a capacitor coupling ratio between the floating gate and the control gate can be raised. Therefore, without increasing the area of a device size, the capacitor coupling ratio can be enhanced to increase the coupling voltage of the floating gate, and to improve the programming/erasing efficiency of the device.
Another object of the present invention is that a gate region and a source/drain of a flash memory cell of the present invention are only separated with a tunneling oxide layer, and the depth of the trench is much larger than the junction depth of the source/drain. Thus, by applying a FN tunneling effect to program/erase a flash memory cell, a short tunnel effect can be avoided, and the programming/erasing of the flash memory cell can be easier to optimize.
A further object of the present invention is to provide a method for manufacturing a flash memory cell formed on a trench. After the trench with a size larger than a channel is formed on a channel region, the trench is filled with a sacrificial layer. Then, after a channel film is formed on the sacrificial layer, the sacrificial layer inside the trench is removed, so that the channel film traverses over the trench as a single-plank bridge, and a hollow region is formed between the channel film and the bottom of the trench. By changing the depth of the hollow region between the channel film and the bottom of the trench, the overlap area between a floating gate and a control gate sequentially formed in the hollow region can be adjusted to improve the capacitor coupling ratio between the floating gate and the control gate.
According to the aforementioned major object, the present invention further provides a structure of a flash memory cell, comprising: a substrate, wherein the substrate comprises an isolation region, a channel region, and a trench located on the isolation region formed thereon, and the size of the isolation region is larger than the size of the channel region, and the entire channel region is covered by the isolation region; a source and a drain located beside two sides of the channel region respectively; a crystallized semiconductor film traversed over a portion of the trench, wherein the crystallized semiconductor film is connected with the source and the drain respectively; an oxide layer surrounding and encompassing the crystallized semiconductor film; a floating gate, wherein the oxide layer is surrounded and encompassed by a portion of the floating gate, and the isolation region and the trench are covered by another portion of the floating gate, and the material of the floating gate is polysilicon; a dielectric layer, wherein the portion of the floating gate is surrounded and encompassed by a portion of the dielectric layer, and another portion of the floating gate is covered by another portion of the dielectric layer; and a control gate, wherein the portion of the dielectric layer is surrounded and encompassed by the control gate, and another portion of the dielectric layer and a portion of the substrate are covered by the control gate, and the material of the control gate is polysilicon or polycide.
According to the further object mentioned above, the present invention further provides a method for manufacturing a flash memory cell, the method comprising: providing a substrate, wherein the substrate comprises an isolation region and a channel region formed thereon, and the size of the isolation region is larger than the size of the channel region, and the entire channel region is covered by the isolation region, and the isolation region is filled with an insulating material; removing a portion of the insulating material in the isolation region to form a trench on the isolation region in the substrate; forming a sacrificial layer to cover the isolation region and the trench, wherein the trench is filled with the sacrificial layer; forming an amorphous semiconductor film to cover the substrate and the sacrificial layer; performing a re-crystallization step to make the amorphous semiconductor film located on the isolation region change into a crystallized semiconductor film, and to make the amorphous semiconductor film covered on the substrate integrate into the substrate, wherein the temperature of the re-crystallization step is between about 500xc2x0 C. and about 600xc2x0 C., and the duration of the re-crystallization step is between about 0.5 hour and about 6 hours; removing a portion of the crystallized semiconductor film to leave another portion of the crystallized semiconductor film located on the channel region, and to expose a portion of the sacrificial layer; removing the sacrificial layer to expose a bottom of the trench, so as to form a hollow region constituted by another portion of the crystallized semiconductor film and the bottom of the trench, and to form a plurality of slots between another portion of the crystallized semiconductor film and the trench; forming an oxide layer to surround and encompass the remaining portion of the crystallized semiconductor film, wherein the oxide layer is a tunneling oxide layer; forming a floating gate to surround and encompass the oxide layer, and to cover a sidewall and a bottom of the hollow region, wherein the material of the floating gate is polysilicon; forming a dielectric layer to cover the floating gate, wherein the dielectric layer is a stacked structure composed of oxide/nitride/oxide; and forming a control gate to cover the dielectric layer, wherein the material of the control gate is polysilicon or polycide. Furthermore, a source and a drain of the flash memory cell of the present invention can be formed before the formation of the amorphous semiconductor film, or after the formation of the control gate, by using, for example, an ion implantation method, to dope ions beside two sides of the channel region.